Cache memories reduce memory access times of large external memories. FIG. 1 illustrates a conventional cache architecture where a cache memory 120 is inserted between one or more processors 110 and a main memory 130. Generally, the main memory 130 is relatively large and slow compared to the cache memory 120. The cache memory 120 contains a copy of portions of the main memory 130. When the processor 110 attempts to read an area of memory, a check is performed to determine if the memory contents are already in the cache memory 120. If the memory contents are in the cache memory 120 (a cache “hit”), the contents are delivered directly to the processor 110. If, however, the memory contents are not in the cache memory 120 (a cache “miss”), a block of main memory 130, consisting of some fixed number of words, is typically read into the cache memory 120 and thereafter delivered to the processor 110.
Cache memories 120 are often implemented using CMOS technology. To achieve lower power and higher performance in CMOS devices, however, there is an increasing trend to reduce the drive supply voltage (Vdd) of the CMOS devices. To maintain performance, a reduction in the drive supply voltage necessitates a reduction in the threshold voltage (Vth), which in turn increases leakage power dissipation exponentially. Since chip transistor counts continue to increase, and every transistor that has power applied will leak irrespective of its switching activity, leakage power is expected to become a significant factor in the total power dissipation of a chip. It has been estimated that the leakage power dissipated by a chip could equal the dynamic power of the chip within three processor generations.
One solution for reducing leakage power is to power down unused devices. M. D. Powell et al., “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) (2000) and Se-Hyun Yang et al., “An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches,” ACM/IEEE International Symposium on High-Performance Computer Architecture (HPCA) (January 2001), propose a micro-architectural technique referred to as a dynamically resizable instruction (DRI) cache and a gated-Vdd circuit-level technique, respectively, to reduce power leakage in static random access memory (SRAM) cells by turning off power to large blocks of the instruction cache.
U.S. patent application Ser. No. 09/865,847, filed May 25, 2001, entitled, “Method and Apparatus for Reducing Leakage Power in a Cache Memory,” incorporated by reference herein, discloses a method and apparatus for reducing leakage power in cache memories by removing the power of individual cache lines that have been inactive for some period of time assuming that these cache lines are unlikely to be accessed in the future. While the disclosed cache decay techniques reduce leakage power dissipation by turning off power to the cache lines that have not been accessed within a specified decay interval, such cache decay techniques will increase the miss rate of the cache (i.e., when a cache line is accessed that has been decayed prematurely). A need therefore exists for an adaptive method and apparatus for reducing leakage power in cache memories that adjusts the decay interval based on the performance of the cache following a cache decay.